Introduction - BCL Molecular 18

BCL Molecular 18
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Order Code


The Molecular word length is 17 bits. By convention, the bits are numbered B17:B1 from left to right and grouped into one pair (B17:B16) and five triples for representation in six octal digits, for example:

17 16 15 14 13 12 11 10 9  8  7  6  5  4  3  2  1
0  1  0  1  0  0  1  1  1  0  0  1  0  1  1  1  0

The above bit-pattern is written as 123456 in octal. All bits set is written as 377777 in octal.

In two's complement binary arithmetic, B17 is the Sign Bit.
For numbers allocated to more than one word, B17 in each low order word is never used.
A double word number has one sign bit followed by 32 binary digits (thus a double word -1 is stored as 377777 177777 in octal).

A word may hold two eight-bit Bytes: B16:B9 is called the Top Byte (octal Mask 177400) and B8:B1 is called the Bottom Byte (octal Mask 000377). B17 is spare:

Each 17-bit memory word has a unique Memory Address of 16 bits (octal range 000000 to 177777), allowing 64K words to be addressed. A word is the smallest (and the largest) memory unit the instruction set can operate on (disc drive and line printer controllers can transfer larger blocks independently via a data channel).

Memory Reference Instructions are limited to the ten low order address bits (B10:B1), each 1K (210) boundary is very significant in programming and it is often useful to give each 1K memory block its own Page Number (in Octal of course, from 00 to 77). Thus the Memory Address 013004 may also be written as 05/1004 to indicate it is Word 1004 of Page 05. Indeed, this is the conventional way of indicating the presence of an absolute address.
Programs are handwritten in pencil on foolscap coding sheets, each sheet holding a "column" of 64 (decimal) memory words (or program "steps").
Thus the above address is sometimes also identified as Page 05 Column 10 Step 04:

Registers and Flags
There are two General Purpose 17-bit registers available to programmers, known as the A-Register and the B-Register.
The A-Register has Memory Address 00/0000 and the B-Register has Memory Address 00/0001. So, to copy the A-Register to the B-Register you either store the A-Register at Memory Address 00/0001 or load the B-Register from Memory Address 00/0000.

The Carry Flag (the C-Flag) is a single bit accessible to programmers. It indicates a carry (or borrow) between B16 and B17 in Memory Reference addition (or subtraction) instructions and also participates in Register SHIFT and ROTATE instructions.

The Greater Than Flag (the GT-Flag) is a single bit accessible to programmers. The Memory Reference instructions CMPA and CMPB set (or clear) the GT-Flag according as the register (excluding B17) is (or is not) greater than the operand.
Do not rely on the hardware setting of the GT-Flag if the comparison may involve negative numbers!

The Switch Register (the SW-Register) is a row of 17 switches mounted on the Control Panel. Programs may read the SW-Register via the ESWRA and ESWRB instructions. The SW-Register may be set manually regardless of the position of the Control Panel's keyswitch.

The Program Counter (the PC-Register) holds the 16-bit Memory Address of the next instruction to be fetched for execution.

The Memory Address Register (the MA-Register) holds the 16-bit Memory Address of the Memory Word being read or written.

Instruction steps
The Processor executes an instruction as illustrated in the flow chart, where the symbolic Instruction Register (IR) holds the 17-bit instruction under execution.
An interrupt is cleared when acknowledged by software. There is one interrupt level; further interrupts remain disabled until re-enabled by an Interrupt ON instruction, which takes effect only after the immediately following instruction (thus enabling the interrupt to be dismissed).
Interrupt priority is determined firstly by software, which should first test for MAINS OFF and ensure all interrupt service routines are kept short. Input/Output devices are grouped together by the Acknowledge Interrupt instruction with their relative priorities (probably) based upon the position of each interface board on the bus.

There is no stack. Subroutine calls are implemented by the JSBR instruction which saves the current PC at the start address of the subroutine. Return from subroutines (and interrupts) is accomplished via an indirect JUMP to the Return Address stored at the head of the subroutine.

At MAINS ON, MA and PC are loaded with the value 000002 and interrupts are disabled. Instruction execution will begin automatically if the control panel keyswitch is at NORMAL.

(C) 2022 Kevin Murrell & The National Museum of Computing
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