Order Code - BCL Molecular 18

BCL Molecular 18
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Words

The Molecular word length is 17 bits. By convention, the bits are numbered B17:B1 from left to right and grouped into one pair (B17:B16) and five triples for representation in six octal digits, for example:

17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1
0  1  0  1  0  0  1  1   1  0  0  1  0  1  1  1  0

The above bit-pattern is written as 123456 in octal. All bits set is written as 377777 in octal.

In two's complement binary arithmetic, B17 is the Sign Bit.
For numbers allocated more than one word, B17 in each low order word is never used.
So a double word number has one sign bit followed by 32 binary digits (thus a double word -1 is stored as 377777 177777 in octal).

A word may hold two eight-bit Bytes: B16:B9 is called the Top Byte (octal Mask 177400) and B8:B1 is called the Bottom Byte (octal Mask 000377). B17 is spare:

Addresses
Each 17-bit memory word has a unique Memory Address of 16 bits (octal range 000000 to 177777), allowing 64K words to be addressed. A word is the smallest (and the largest) memory unit the instruction set can operate on (disc drive and line printer controllers can transfer larger blocks independently via a data channel).
Because Memory Reference Instructions are limited to the ten low order address bits (B10:B1), each 1K (210) boundary is very significant in programming and it is often useful to give each 1K memory block its own Page Number (in Octal of course, from 00 to 77). Thus the Memory Address 013004 may also be written as 05/1004 to indicate it is Word 1004 of Page 05. Indeed, this is the conventional way of indicating the presence of an absolute address.
Programs are handwritten in pencil on foolscap coding sheets, each sheet holding a "column" of 64 (decimal) memory words (or program "steps").
Thus the above address is sometimes also identified as Page 05 Column 10 Step 04:

Registers and Flags
There are two General Purpose 17-bit registers available to programmers, known as the A-Register and the B-Register.
The A-Register has Memory Address 00/0000 and the B-Register has Memory Address 00/0001. So, to copy the A-Register to the B-Register you either store the A-Register at Memory Address 00/0001 or load the B-Register from Memory Address 00/0000.
The Carry Flag (the C-Flag) is a single bit accessible to programmers. It indicates a carry (or borrow) between B16 and B17 in Memory Reference addition (or subtraction) instructions and may participate in Register SHIFT and ROTATE instructions.
The Greater Than Flag (the GT-Flag) is a single bit accessible to programmers. The Memory Reference instructions CMPA and CMPB set (or clear) the GT-Flag according as the register (excluding B17) is (or is not) greater than the operand.
Do not rely on the hardware setting of the GT-Flag if the comparison may involve negative numbers!
The Switch Register (the SW-Register) is a row of 17 switches mounted on the Control Panel. Programs may read the SW-Register via the ESWRA and ESWRB instructions. The SW-Register may be set manually regardless of the position of the Control Panel's keyswitch.
The Program Counter (the PC-Register) holds the 16-bit Memory Address of the next instruction to be fetched for execution.
The Memory Address Register (the MA-Register) holds the 16-bit Memory Address of the Memory Word being read or written.

Instruction steps
The Processor executes an instruction as illustrated in the following flow chart, where the symbolic Instruction Register (IR) holds the 17-bit instruction under execution:
An interrupt is cleared when acknowledged by software. There is one interrupt level; further interrupts remain disabled until re-enabled by an Interrupt ON instruction, which takes effect only after the immediately following instruction (thus enabling the interrupt to be dismissed).
Interrupt priority is determined firstly by software, which should first test for MAINS OFF and ensure all interrupt service routines are kept short. Input/Output devices are grouped together by the Acknowledge Interrupt instruction with their relative priorities (probably) based upon the position of each interface board on the bus.
There is no stack. Subroutine calls are implemented by the JSBR instruction as shown above. Returns from subroutines (and interrupts) are accomplished via an indirect JUMP to the Return Address stored at the head of the subroutine.
At MAINS ON, MA and PC are loaded with the value 000002 and interrupts are disabled. Instruction execution will begin automatically if the control panel keyswitch is at NORMAL.

Privileged Instructions
These instructions (NOOP excepted) should be used only by the Operating System. The designation "privileged" is purely symbolic; there is no hardware protection to prevent their use by any application.

000000
NOOP No operation
000001 HALT (requires manual resumption from Control Panel)
000002 MASK Never used
000003 Acknowledge Interrupt Loads B-Register with highest priority interrupting Device Code
000004 Interrupt ON Enables interrupts after completion of the immediately following instruction
000005 Interrupt OFF Disables interrupts
000006 Skip if Interrupt ON Tests interrupt state
000007 Skip if Interrupt OFF Tests interrupt state
000010 Skip if MAINS OFF Tests and clears Mains Off interrupt
000011 Skip if MAINS ON Tests and clears Mains On interrupt
000012 Skip if PARITY Tests and clears Parity interrupt
000013 Skip if PROTECTION Never used
000014 Skip if BOUNDARY Never used
000015 Skip if MA=SW Tests and clears MA=SW interrupt
000016 Skip if CONTINUOUS INTERRUPT Tests and clear Continuous Interrupt
000017 Input/Output RESET (allow 1 second for devices to react)

Register Instructions
1716151413121110 9 8 7 6 5 4 3 2 100000011=A reg
0=B regCLC1=LEFT
0=RIGHTSHIFTROTATEwith
CARRYDECINCSKIP
if
MSB=0SKIP
if
LSB=000000101=A reg
0=B regCLEAROne's
COMPCLCCOMPCSKIPSWAPCLEAR
SIGNCOMP
SIGNESWR00000111=A reg
0=B reg1=TRUE
0=FALSESKIP
if
NEGSKIP
if
NOT 0SKIP
if
CARRYCLCSKIP
if
GTCLGTCLEAROne's
COMP

Micro-Programming Rules
Instructions on the same row in the above table may be combined in a single instruction, subject to the following:
  • Instructions will be executed in order from the left, except CLEAR SIGN which on some machines precedes CLEAR.
  • If skips are combined, the skip will occur only if all conditions are fulfilled, except if AMSB and ALSB (or BMSB and BLSB) are combined the skip will occur if either or both conditions are met.
  • The effect of combining SHIFT and ROTATE or INC and DEC is undefined.
For example:
005006 combines CLSA and COMPSA in that order to set the sign (B17) of the A-Register.
007502 combines AN0 and CLA to test for zero in, then clear, the A-Register.

A-RegisterB-RegisterInstruction
003001ALSB
002001BLSBSkip if B1=0
003002AMSB
002002BMSBSkip if B16=0
007600ANEG
006600BNEGSkip if B17=1
007500AN0
006500BN0Skip if not zero
007200APOS
006200BPOSSkip if B17=0
007100A0006100B0
Skip if zero
007002
CLA006002
CLBClear
002400CLC  Clear CARRY Flag
006004CLGT  Clear GREATER THAN Flag
005004CLSA
004004CLSBClear B17 (Sign bit)
007001
COMPA006001
COMPBOnes-Complement
004040COMPC  Complement CARRY Flag
005002COMPSA
004002COMPSBComplement B17 (Sign bit)
003010DECA
002010DECBDecrement by one
005001ESWRA
004001ESWRBEnter Switch Register (read Switches into)
003004INCA
002004INCBIncrement by one
003240LRA
002240LRBRotate Left by one (excluding B17)
003260LRAC
002260LRBCRotate Left by one including CARRY (excluding B17)
001600+nLRAn000600+nLRBnRotate Left by n (excluding B17)
003300LSA002300LSBLeft Shift by one (excluding B17)
001700+nLSAn000700+nLSBnLeft Shift by n (excluding B17)
003040RRA
002040RRBRotate Right by one (excluding B17)
003060RRAC
002060RRBCRotate Right by one including CARRY (excluding B17)
001400+nRRAn000400+nRRBnRotate Right by n (excluding B17)
003100RSA002100RSBRight Shift by one (excluding B17)
001500+nRSAn000500+nRSBnRight Shift by n (excluding B17)
001520+nRSAAn000520+nRSABnRight Shift by n Arithmetic
001001SETGT  Set GREATER THAN Flag
005006SETSA
004006SETSBSet B17 (Sign bit)
006440SKC  Skip if CARRY Flag=1
006410SKGT  Skip if GREATER THAN Flag=1
004020SKIP  Skip unconditionally
006040
SKNC  Skip if CARRY Flag=0
006010SKNGT  Skip if GREATER THAN Flag=0
005010SWAPA004010SWAPBSwap Bytes
The maximum value of n is 15 (decimal).
Execution time 1.4 microseconds, except SETGT (1.2 μs) and multiple shifts/rotates (1.6 μs if n<=1; 3.2 μs if n<=6; 4.8 μs if n<=11; 6.4 μs otherwise).

Input/ Output Instructions
I/O instructions should only be executed by the Operating System or system software.
I/O devices may have up to three 17-bit Device Registers, accessible to the programmer, implemented by their hardware interface. By convention, Device Register 3 is the Status Register.
All I/O devices also have a BUSY flag and a DONE flag. Software starts a device by setting its BUSY flag (after loading relevant device registers); the device signals an INTERRUPT REQUEST whilst its DONE flag is set (unless disabled by the Current Mask).
1716151413121110 9 8 7 6 5 4 3 2 1000011=A-Reg
0=B-RegFUNCTION
or
SKIP CONDITIONMODEDEVICE CODE
Mode (B9:B7)
B9:B7MnemonicAction1DATI1Read Device Register 12DATI2Read Device Register 23DATI3Read Device Register 34DATO1Write Device Register 15DATO2Write Device Register 26DATO3Write Device Register 37SKIPTest for SKIP CONDITION
Function or Skip Condition (B11:B10)
B11:B10FunctionSKIP IF0No OperationBUSY1START (Set BUSY, Clear DONE)NOT BUSY2STOP (Clear BUSY, Clear DONE)DONE3IOPLS (Input/Output Pulse)NOT DONE
Device Codes (B6:B1)
InOutStandard Assignment2060Alpha-numeric Keyboard5040Visual Display Unit 30Line Printer 34Serial Printer6667IBM I/O Writer1133Paper Tape7070Disc

Memory Reference Instructions

Memory Reference instructions can directly access memory only within the Current Page (i.e. the page within which the instruction itself is stored) or within the lowest Page (i.e. Page 00, often called Zero Page, comprising Words 00/0000 to 00/1777).
But that word may contain the 16-bit address of any word in memory and the Memory Reference instruction can indirectly access that word through the "pointer". If the pointer's B17 is set, then the target word is itself a pointer and so on indefinitely.  It's left to the programmer to ensure that such a chain does not form a closed loop.

Operation Code MnemonicInstruction
02 JUMP Jump unconditionally
03 JSBR Jump to Subroutine
04 INSZ Increment by one, Skip if result is zero
05 DESZ Decrement by one, Skip if result is zero
06 ANDA AND into A-Register
07 IORA Inclusive OR into A-Register
10 XORA Exclusive OR into A-Register
11 ADA Add to A-Register
12 ADB Add to B-Register
13 SFA Subtract from A-Register
14 SFB Subtract from B-Register
15 ADAC Add to A-Register with CARRY
16 ADBC Add to B-Register with CARRY
17 SFAC Subtract from A-Register with CARRY
20 SFBC Subtract from B-Register with CARRY
21 LDA Load into A-Register
22 LDB Load into B-Register
23 CMPA Compare with A-Register, Skip if B17:B1 unequal (see also GT-Flag)
24 CMPB Compare with B-Register, Skip if B17:B1 unequal (see also GT-Flag)
25 STA Store A-Register
26 STB Store B-Register

(C) 2022 Kevin Murrell & The National Museum of Computing
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