Programmers' Reference

Hardware

Words

The Molecular word length is 17 bits. By convention, the bits are numbered B17:B1 from left to right and grouped into one pair (B17:B16) and five triples for representation in six octal digits, for example:

The above bit-pattern is written as 123456 in octal. All bits set is written as 377777 in octal.

In two's complement binary arithmetic, B17 is the Sign Bit. For numbers allocated more than one word, B17 in each low order word is never used. So a double word number has one sign bit followed by 32 binary digits (thus a double word -1 is stored as 377777 177777 in octal).

A word may hold two eight-bit Bytes: B16:B9 is called the Top Byte (octal Mask 177400) and B8:B1 is called the Bottom Byte (octal Mask 000377). B17 is spare.

Addresses

Each 17-bit memory word has a unique Memory Address of 16 bits (octal range 000000 to 177777), allowing  64K words to be addressed. A word is the smallest (and the largest) memory unit the instruction set can operate on (disc drives and line printers can transfer larger blocks independently via a data channel).

Because Memory Reference Instructions are limited to the ten low order address bits (B10:B1), each 1K (2¹⁰) boundary is very significant in programming and it is often useful to give each 1K memory block its own Page Number (in Octal of course, from 00 to 77). Thus the Memory Address 013004 may also be written as 05/1004 to indicate it is Word 1004 of Page 05. Indeed, this is the conventional way of indicating the presence of an address.

• Programs are handwritten in pencil on foolscap coding sheets, each sheet holding a "column" of 64 (decimal) memory words (or program "steps"). Thus the above address is sometimes also identified as Page 05 Column 10 Step 04:

Memory Reference instructions can directly access memory only within the Current Page (i.e. the page within which the instruction itself is stored) or within the lowest Page (i.e. Page 00, often called Zero Page, comprising Words 00/0000 to 00/1777). But such a word may contain the 16-bit address of any word in memory and the Memory Reference instruction can indirectly access that word through the "pointer". If the pointer's B17 is set, then the target word is itself a pointer and so on indefinitely. It's left to the programmer to ensure that such a chain does not form a closed loop.

Registers and Flags

There are two General Purpose 17-bit registers available to programmers, known as the A-Register and the B-Register.

• The A-Register has Memory Address 00/0000 and the B-Register has Memory Address 00/0001. So, to copy the A-Register to the B-Register you either store the A-Register at Memory Address 00/0001 or load the B-Register from Memory Address 00/0000.

The Carry Flag (the C-Flag) is a single bit accessible to programmers. It indicates a carry (or borrow) between B16 and B17 in Memory Reference addition (or subtraction) instructions and may participate in Register SHIFT and ROTATE instructions.

The Greater Than Flag (the GT-Flag) is a single bit accessible to programmers. The Memory Reference instructions CMPA and CMPB set (or clear) the GT-Flag according as the register (excluding B17) is (or is not) greater than the operand.

• Do not rely on the hardware setting of the GT-Flag if the comparison may involve negative numbers!

The Switch Register (the SW-Register) is a row of 17 switches mounted on the Control Panel. Programs may read the SW-Register via the ESWRA and ESWRB instructions. The SW-Register may be set manually regardless of the position of the Control Panel's keyswitch.

The Program Counter (the PC-Register) holds the 16-bit Memory Address of the next instruction to be fetched for execution.

The Memory Address Register (the MA-Register) holds the 16-bit Memory Address of the Memory Word being read or written.

The Instruction Register (IR) holds the 17-bit Instruction under execution.

Instruction steps

The Processor executes an instruction in the following steps:

1. MA is loaded from PC.
2. PC is incremented by one (all instructions are exactly one word long).
3. IR is loaded from the memory word addressed by MA.
4. If IR holds a Memory Reference instruction, MA is loaded with the operand's address (working to the end of any indirect pointer chain as necessary).
5. If IR holds a JSBR instruction, PC is stored at the memory word addressed by MA.
6. If IR holds a JSBR instruction, or a JUMP instruction, PC is loaded from MA.
7. If IR holds a JSBR instruction, or a SKIP type instruction in which the SKIP condition is fulfilled, PC is incremented by one a second time.

The Processor takes an interrupt by executing it as an instruction from step 4 above, after loading IR directly with the instruction JSBR Z 0002 (032002).

There is no stack. Subroutine calls are implemented by the JSBR instruction as described above. Returns from subroutines (and interrupts) are accomplished via an indirect JUMP to the Return Address stored (at step 5 above) at the head of the subroutine.

At MAINS ON, MA and PC are loaded with the value 000002 and interrupts are disabled. Instruction execution will begin automatically if the control panel keyswitch is at NORMAL.

Privileged Instructions

These instructions (NOOP excepted) should be used only by the Operating System.

Register Instructions

Micro-Programming Rules

Instructions on the same row in the above table may be combined in a single instruction, subject to the following:

• Instructions will be executed in order from the left, except CLEAR SIGN which on some machines precedes CLEAR.
• If skips are combined, the skip will occur only if all conditions are fulfilled, except if AMSB and ALSB (or BMSB and BLSB) are combined the skip will occur if either or both conditions are met.
• The effect of combining SHIFT and ROTATE or INC and DEC is undefined.

For example:
005006 combines CLSA and COMPSA in that order to set the sign (B17) of the A-Register.
007502 combines AN0 and CLA to test for zero in, then clear, the A-Register.

The maximum value of n is 15 (decimal).

Execution time 1.4 microseconds, except SETGT (1.2 µs) and multiple shifts/rotates (1.6 µs if n<=1; 3.2 µs if n<=6; 4.8 µs if n<=11; 6.4 µs otherwise).

Input/ Output Instructions

I/O instructions should only be executed by the Operating System or system software.

I/O devices may have up to three 17-bit Device Registers, accessible to the programmer, implemented by their hardware interface. By convention, Device Register 3 is the Status Register.

All I/O devices also have a BUSY flag and a DONE flag. Software starts a device by setting its BUSY flag (after loading relevant device registers); the device signals an INTERRUPT REQUEST whilst its DONE flag is set (unless disabled by the Current Mask).

Mode

Function or Skip Condition

Device Codes

Memory Reference Instructions

Each level of indirect addressing adds 1.2 µ-sec to the above instruction timings.

Software

Standard Core Locations

The Commandment

Thou shalt not patch.